Layout and verification of complex integrated analogue/mixed signal CMOS circuits and blocks * Technical project leadership including planning and scheduling tasks, coordinate the tasks for the project layout team * Deep technical knowledge and knowledge sharing for PMIC relevant layout strategies like isolation strategy, ballout optimization for power, power device routing, power flow and EMIR verification support * 15+ years of experience in analog and mixed signal integrated circuit layout * Knowledge of analog and mixed signal blocks (e.g. ADC, DAC, LDO's, LNA's, PGA, Bandgap circuits…) and layout techniques (e.g. matching, shielding, star point routing…) * Knowledge on ESD, Latch Up effects and the Layout techniques to prevent problems and possible layout solutions to prevent IR-Drop, Voltage Drop * Deep experience in debugging check results (e.g. Design Rule Check, Layout versus Schematic…) * ams-OSRAM AG
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