The Senior Principal Mixed-Signal Verification Engineer leads and mentors a distributed team of Mixed Signal Verification Engineers, ensuring technical excellence, consistent methodologies and continuous people development and knowledge sharing across all sites. * Builds, extends, and maintains DMS verification environments using SystemVerilog and UVM MS, including testbenches, mixed signal assertions, critical scenarios, and coverage. * 10+ years of experience in analog or mixed-signal circuit design or analog verification with direct involvement in projects through tape-out or product completion - Also designs and maintains the mixed signal regression infrastructure (capacity, debugging, failure analysis) * Analyzes schematics, predicts circuit behavior, and solves complex analog or mixed signal problems independently
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