Develop and maintain Synopsys IC Validator (ICV), Siemens Calibre, Cadence PVS rule decks for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and antenna verification across multiple semiconductor technologies * Execute physical signoff verification flows using Synopsys IC Validator, Simens Calibre, Cadence PVS and analyze verification results to ensure tape-out readiness and compliance with foundry requirements * Investigate and resolve complex verification violations by performing root-cause analysis and collaborating closely with , circuit designers, and technology teams * Develop automation and regression frameworks to improve verification efficiency, rule quality, runtime performance, and result tracking * Integrate verification results into the overall signoff process, including DRC, LVS, ERC, antenna, DFM, and parasiti
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